You don’t have to look very far in the semiconductor world before you see the word “scaling.” Perhaps you read an industry news article headline about transistor scaling – how those nearly nanoscale components are shrinking even smaller in size down to the atomic scale. Or maybe you heard a reference to memory capacity scaling – how our favorite mobile devices can store more high-resolution videos. Whatever the context, scaling is almost always synonymous with “making progress.”
That progress is achieved through shrinking device footprint, growing in the third dimension, and incorporating new materials and innovative architectures. These technology advances enable the digital era we live in today. Over the years, scaling has produced devices that have dramatically changed nearly every aspect of our daily lives, putting enormous amounts of digital information at our fingertips.
The phenomenon of semiconductor scaling has a particularly famous description: Moore’s Law. Originally meant as an economic observation, it predicts the doubling of chip component densities every 2 years. For decades, the industry kept on track by shrinking a key (or “critical”) component dimension through advances in lithography and plasma etching – the processes by which a pattern is defined on the wafer surface and transferred into the underlying material. That critical dimension was frequently the transistor gate length dimension. For example, the 0.5 µm technology node produced a transistor with 0.5 µm gate length. Over the years, the technology node definition has evolved and is now considered more of a generational name rather than a measure of any key dimension. What remains the same is our expectation that node scaling will bring better device performance and greater power efficiency and cost less to build.
At around the 20 nm node, high-performance transistors reached a scaling limit. The industry couldn’t laterally shrink planar transistors any smaller without causing other problems, which drove engineers to look at other transistor designs. The three-dimensional finFET geometry raises key transistor components above the silicon wafer plane to enable shrinking the device footprint without a detrimental reduction in transistor channel volume. FinFET scaling reduces lateral dimensions to increase device density per unit area while increasing fin height as a way to improve device performance.
To continue transistor scaling and deliver higher performance, lower power consumption, and lower cost devices, silicon has been alloyed with germanium but additional new materials may be needed to extend finFET technologies beyond the 5 nm node. Alternately, new architectures such as stacked nanosheets and nanowires may be the answer. Manufacturing these structures will almost certainly involve greater use of atomic layer deposition and etch processes to achieve the scaled dimensions.
As transistors shrink in size, so must the metal lines that connect them within the overall high-rise architecture of the multilevel interconnect stack. With successive generations, these local interconnects have become both narrower and closer together to the point where the incumbent copper interconnects are facing significant challenges to further scaling. For example, further decreases to the line width or height would dramatically increase the electrical resistance of the line. Manufacturers are looking to reduce the amount of room currently needed by the relatively high-resistivity barrier and liner layers that clad the interconnect metal wiring, perhaps by using a new barrier or liner materials. Another possibility is to replace or alloy copper with another metal that does not require a barrier.
Scaling in 3D NAND memory capacity is achieved in a different way: by adding vertical layers. In this memory structure, cell density increases directly with the number of layers in the stack. Early 3D NAND structures were made using 24 layer pairs; today, chips with 96-layer structures are in volume production, and even taller stacks are on the horizon. Each of these layers must be highly uniform and extremely smooth and have good adhesion to the one below — challenges that increase with the number of layers.
Continued scaling through additional layers will present even greater complexity during subsequent processing steps such as high-aspect ratio memory hole etch, staircase definition, and word line fill with tungsten. The increasingly longer channels will eventually become limited by electron mobility, which affects device performance. Work is underway to ensure key deposition and etch processes can support future generations.
Today’s state-of-the-art chips are arguably the most sophisticated devices ever designed and produced, and they are a direct result of decades-long scaling efforts. The performance and cost benefits of shrinking devices laterally and expanding them in the vertical dimension has required significant advances in semiconductor manufacturing equipment, and increasing collaboration between equipment suppliers and chip makers.
Semiconductor scaling has changed how we work, play, commute, and communicate, and we have every expectation that the pace of innovation will continue with “More Moore” scaling. “More than Moore” strategies, which integrate different kinds of technologies in a variety of architectures and systems provide another path for advancing the industry. Both “More Moore” and “More than Moore” schemes will be needed to deliver the diverse, ever faster and more powerful capabilities fueling our smarter, more connected world.