Ever open the body of your smartphone (perhaps unintentionally) and see small, black rectangles stuck on a circuit board? Those black rectangles are packaged chips. The external chip structure protects the fragile integrated circuits inside, as well as dissipates heat, keeps chips isolated from each other, and, importantly, provides connection to the circuit board and other elements. The manufacturing steps involved in creating these protective structures and connections are collectively known as “packaging.” This activity has seen revolutionary changes in recent years, propelled by the drive for smaller and more powerful chips.
Here we take a look at some of the strategies that enable next-generation advanced packaging, including wafer-level packaging, bumping, redistribution layers, fan out, and through-silicon vias. These are great examples of applying front-end wafer manufacturing technologies (such as deposition, etch, and clean) to back-end processing.
In conventional packaging, the finished wafer is cut up, or diced, into individual chips, which are then bonded and encapsulated. Wafer-level packaging (WLP), as its name implies, involves packaging the die while it is still on the wafer: protective layers may be bonded to the top and/or bottom of the wafer, then electrical connections are prepared and the wafer is diced into individual chips. To provide a baking analogy, traditional packaging is similar to frosting individual cupcakes, while WLP is like frosting a whole cake and then slicing it into pieces. Because the sides are not coated with WLP, the resulting packaged chip is small in size (roughly the same size as the chip itself), an important consideration in footprint-sensitive devices such as our smartphones. Other advantages include streamlined manufacturing and the ability to test chip functionality before dicing.
One of the simplest electrical connections between a chip and the circuit board can be made with small balls of electrically conductive material, called bumps. A bumped die can then be flipped upside down and aligned so that the bumps connect with matching pads on the board. Flip chip bonding has several advantages over traditional wire bonding, including small package size and greater device speed.
Bumping can be performed by extending conventional wafer fabrication methods. After the chips are made, underbump metallization (UBM) pads are created to connect to the chip circuitry, and bumps are then deposited on the pads. Solder is the most commonly used bumping material, although alternative materials – such as gold, copper, or cobalt – can also be used depending on the application. For high-density interconnects or fine-pitch applications, copper pillars can be used. While solder bumps spread during the joining process, copper pillars retain their shape, which allows them to be placed much more closely together.
Relocating, or redistributing, contact points is another technology that can be done efficiently at the wafer level. A redistribution layer (RDL) is used to reroute connections to desired locations. For example, a bump array located in the center of a chip can be redistributed to positions near the chip edge. The ability to redistribute points can enable higher contact density and enable subsequent packaging steps. This “fan-in” process also creates one of the smallest packages available.
The redistribution process adds another set of layers over the wafer surface. A dielectric film is deposited for electrical isolation, then the original bond pads are exposed. Metal lines are deposited to relocate the pads to desired locations, and underbump metallization layers are built to support the solder (or other metal) bumps.
The redistribution process can also be used to spread or “fan out” the connection points. This may be needed, for example, when the chip shrinks in size while requiring the same number of contact points. One solution is to fan out the contacts beyond the dimensions of the chip. A compelling application of this technology is the improved electrical and thermal performance along with a reduction in overall package height.
Fan-out wafer-level packaging (FOWLP) typically involves first dicing the front-end-processed wafer into individual die. These die are then spaced apart on a carrier structure, and the gaps are filled in to form a reconstituted wafer. Once the artificial wafer has been built, the contacts can be redistributed beyond the perimeter of the original die using WLP processing.
While bumping and RDL may reduce the surface area chips use on a circuit board, space usage can be even more efficient when chips are stacked. Even better, stacking is a strategy that improves the electrical performance of multiple chips. Wire bonding is one way to create stacked assemblies, and silicon vias (TSVs) have emerged as an attractive alternative that can offer a smaller form factor. A TSV is an electrical connection through the entire thickness of the chip, creating the shortest possible path from one side of the chip to the other. The short interconnect length between chips can also mean lower power consumption and greater bandwidth.
In one common way to create TSVs, the vias (holes) are etched from the front side of the wafer to a certain depth. These are then isolated and filled by depositing a conductive material, typically copper. After chip fabrication is complete, the wafer is thinned from the back side to expose the vias, and metal is deposited on the backside of the wafer to complete the TSV interconnection.
No longer an afterthought in the semiconductor manufacturing process, packaging has exploded with innovation and complexity. In particular, wafer-level packaging has experienced tremendous advancements in materials, processes, and equipment, enabling WLP to become one of the fastest growing chip packaging technologies. Bumping, redistribution layers, fan out, through-silicon vias, and other techniques have contributed to the small-form-factor chips with powerful, high-speed functionality that we consumers expect in our mobile electronics. We look forward to seeing the next generation of semiconductor devices enabled by leading-edge packaging technologies.