Have you ever wondered how everyday electronics, like smartphones and tablets, pack so much functionality into such relatively small and lightweight packages? If so, here’s your chance to learn a bit more about one of the key technologies behind making these complex devices so compact – multiple patterning – which was also one of the hot topics at the recent SPIE Advanced Lithography Symposium.
For decades, one of the main ways the industry kept chip innovation on track with Moore’s Law was by scaling lithography capability to produce ever-smaller feature dimensions. In conventional lithography, a wafer is coated with a light-sensitive material called photoresist. Light is then streamed through a photomask (a pattern of transparent and opaque areas), exposing the photoresist in some places, but not in others. The exposed regions are then etched away, while covered areas remain protected (in the case of positive photoresist). The end result is a set of features whose size and density are determined by the original photoresist pattern.
Today’s advanced chip designs have smaller and more dense features than can be created using available lithography capability. Fortunately, advanced patterning techniques have been devised to work around these limitations by using multiple patterns of larger dimensions to obtain smaller and/or more tightly packed features.
The simplest form of multiple patterning is double patterning, which increases feature density by a factor of two. One of the most widely adopted double patterning schemes is double exposure/double etch, also known as litho-etch-litho-etch, or LELE. This technique splits a given pattern into two less dense parts. The first pattern is transferred onto an underlying hardmask through exposure of photoresist during lithography, followed by etching the hardmask. The second pattern is then aligned to the first and transferred onto the hardmask through another exposure of photoresist and hardmask etch. The end result is a pattern that is twice as dense as the original.
Another double patterning scheme that is gaining a lot of attention is the self-aligned spacer technique. In this scheme, spacers are formed on the sidewalls of a pre-defined feature, called a mandrel, through deposition and etch process steps. Next, the mandrel is removed by an additional etch step, leaving only the spacers, which are then used to define the desired final structures. Because there are two spacers for each mandrel, the feature density is doubled.
Examples of self-aligned double patterning (SADP) applications include formation of fins in FinFET technology, lines and spaces for interconnect levels, and bitline/wordline features in memory devices. Although this technique often requires additional processing steps, one key advantage is that it avoids variations caused by mask misalignment that can occur during LELE double patterning. Because the critical dimensions are defined by spacer formation and mandrel removal, stringent process control for the deposition and etch steps is absolutely essential.
One attribute of the self-aligned spacer technique is that, in principle, it can double the pattern density indefinitely by repeating the spacer formation and pattern transfer steps. For example, doubling a double patterning scheme results in quadruple patterning. While SADP with current 193 nm immersion lithography can achieve a half-pitch resolution of ~20 nm, self-aligned quadruple patterning (SAQP) can achieve a half-pitch resolution of ~10 nm. With such small feature dimensions, minimizing variability of the enabling deposition and etch steps is critical. To allow continued scaling, production-worthy processes that deliver atomic-scale control, such as Lam’s atomic layer deposition (ALD) and atomic layer etch (ALE) technologies, will become even more important.
Looking ahead, we expect multiple patterning will continue to play a critical role in enabling chipmakers to deliver the ever-smaller, more capable devices we have come to expect from this exciting industry.