“Data is giving rise to a new economy” – The Economist (2017). This compelling reality makes the continued development of high-capacity data storage technologies like 3D NAND ever more important. With this in mind, Lam executives shared their perspectives on the growing need for vertical scaling in a “Vertical Reality” fireside chat. Held during the August 2017 Flash Memory Summit, topics spanned the challenges and opportunities for 3D NAND, the 3D evolution of memory and logic, and the enabling roles that storage and memory play in our data-driven world.
Lam chief operating officer Tim Archer opened the discussion by sharing just one example of increasing data generation: Lam’s equipment today has numerous sensors that create gigabytes of data from every wafer processed. For the millions of wafers that chipmakers process every year, it’s a huge challenge to determine how best to transmit and analyze that information and extract “actionable intelligence from the data that’s collected,” Tim said. “[The] entire process of transmitting, storing, and analyzing data is creating tremendous demand for semiconductors. This is not just a high-tech industry issue. This is something that every company in virtually every industry is trying to figure out – how to better utilize data to expand their business.”
The implications of a data-driven world are many and challenging. In particular, the enabling semiconductors that provide its backbone have to deliver higher performance for the big data age. Rick Gottscho, Lam’s corporate chief technology officer, described performance scaling as achieving greater device speed and density and lower power usage and manufacturing cost. Traditionally, that has been driven through shrinking with single-pass lithography. More recently, compensation for lithography resolution limitations has led to the industry adoption of multi-pass lithography, which is deposition- and etch-intensive.
“I think people have a misunderstanding that we can’t make things smaller.We are making things smaller…but making things smaller is just no longer good enough,” Rick explained. The cost and speed benefits of scaling are lower than historical levels. For logic, reducing power consumption is a significant problem, in particular for mobile products. In memory (DRAM), it becomes more difficult to store charge in a smaller and smaller capacitor, and there is more leakage in smaller and smaller devices. In storage (primarily 2D NAND flash), smaller devices can’t store enough charge and can interfere with each other.
“The solution is vertical scaling. If you can’t make things smaller and closer together, you just go up,” Rick said, adding that we are focused on “three really critical processes” specific to 3D NAND: deposition of the mold stack, drilling (etching) of the memory hole, and inside-out filling of the replacement-gate tungsten word lines. For high-performing devices, exceptional uniformity of the deposited layers, precise etch of the high aspect ratio holes, and complete word line fill are needed.
The key to extending 3D NAND is being able to stack more layers in a single pass before needing to start a new stack on top. As layers are added, the challenges of managing film thickness uniformity and stress during deposition and also hole profile consistency during etch increase significantly. To clarify, this is not chip stacking – it’s hundreds of layers on top of hundreds of layers on the same wafer – really challenging technology. “Right now, we’re very comfortable with more than 100 layers, and we see that being extended,” Rick added. “When you put all that together with the progress we’re making and the technical solutions in the pipeline, we think this is going to go on for at least another 10 years.”
While extending the storage component of data management is covered for some time with vertical scaling, DRAM (memory) and logic (computing) are expected to take rather different paths. According to Rick, DRAM still has a couple more generations to go, and then it will be replaced by new types of memory like phase change (PCRAM or PCM), magnetic (MRAM), and resistive (RRAM) that are currently in development. All non-volatile, these technologies will provide a major reduction in power consumption. As with NAND for storage, these new memory devices will be built up into 3D arrays. Additionally, they involve new materials that are difficult to process and require the development of new deposition and etch capabilities.
Next, there will be “a convergence of memory and logic together,” Rick said. Going from one chip to another consumes a lot of power and time, so putting them on the same chip will improve performance. Rick predicted that “we’ll probably see computing going from the digital realm back into the analog realm.” Instead of data being stored in memory as digital quantities, the actual analog data will be recorded. In other words, Rick clarified, “the memory device actually becomes a processor” and again, it’s a three-dimensional structure.
It’s an exciting time to be a contributor to the new capabilities empowering the smart use of big data. “We believe etch, deposition, and clean really represent the three fundamental building blocks for vertical scaling,” Tim said. Together with our customers, we have much opportunity ahead in developing the 3D NAND, new memory, logic, and other devices that lay the foundation of the new data economy.