Atomic layer etching and deposition processes offer atomic scale control through the use of self-limiting reactions. Yang Pan, corporate vice president of advanced technology development, shares his thoughts on this topic with Semiconductor Digest.
Every advance in technology node has required tighter control over manufacturing process variability. The most advanced processes are now creating fin widths of only 7 nm, a little more than 30 silicon atoms. Semiconductor manufacturing has crossed the threshold from nano-scale to atomic scale processing. Engineers must now be concerned with dimensional variability in the structures they create equivalent to only a few atoms. The problem is compounded by the increased number of processing steps in advanced processes like multiple patterning, which further constrains the allowable variation per step. Adding to the level of complexity and challenge are the complicated geometries in 3D NAND and finFET structures.
Controlling variability has always been a key challenge from the semiconductor industry, as it directly impacts performance, yield, and reliability, and thus, has significant economic consequences. Process-induced variability comes from multiple sources across the die, wafer, and tool. One way to gain control of variability is through the application of technologies such as atomic layer deposition (ALD) and atomic layer etching (ALE), which are inherently more precise then conventional plasma methods.
Atomic layer processing, including both deposition and etch solutions, share some characteristics. Unlike continuous processes, they proceed in cycles, with each cycle adding or removing a finite and fixed number of molecular layers. A cycle is divided into half cycles, each of which is a distinct, self-limiting process that prepares the surface for the next half cycle. For example, in SiO2 deposition (fig 1,2), the first half cycle involves adsorption of oxygen atoms, which is self-limited by the availability of binding sites. Excess oxygen is then purged from the chamber, and the surface is exposed to a source of silicon atoms, which react with the adsorbed oxygen to create a layer of SiO2. Again, the half cycle process is self-limited, in this case by the availability of oxygen. The self-limiting, sequential nature of ALD is widely used in HVM of advanced logic in memory chips.
Like its deposition counterpart, ALE proceeds in half cycles that are self-limiting. In a silicon etch process, for example, the first half cycle exposes the silicon surface to chlorine, which binds to the first layer of silicon atoms and weakens their bonds to their underlying neighbors (fig 2). The process stops when the surface is saturated, and then unused chlorine is purged. The second half cycle bombards the modified surface with argon ions, which remove the chlorine activated top silicon layer, but not the underlying silicon. When the chlorinated layer is gone, the cycle is complete and a thin layer of material has been precisely removed.
Historically, the integration of ALE into high-volume semiconductor manufacturing has been limited by its low etch rates relative to continuous etch processes. Two factors have combines to reduce the impact of lower etch rates on overall throughput. The first is the continuing decrease in feature sizes, which has reduced the amount of materials to be removed and the number of ALE cycles required. The second comprises advances in ALE technology, such as rapid gas exchange techniques, which have significantly increased cycling speed. The increasing need for atomic-scale control on smaller features has focused renewed attention on the technique. ALE also offers other important benefits, including improved directionality (anisotropy), smoother surface, better material selectivity, flatter etch fronts with less surface damage and mixing, elimination of pattern density-dependent loading effect and improved cross wafer uniformity.
Continue reading the article on page 9 of Semiconductor Digest.