Multiple patterning is an innovative approach to scaling semiconductors, but it also poses significant challenges controlling process variations. Lam’s Rick Gottscho, executive vice president of Global Products, shares his thoughts on this important topic with EE Times.
Multiple patterning is a method for enhancing feature density by producing finer resolution than can be achieved with a single lithographic pass. It has been proven in volume production as an effective method for pitch-shrinking, with 2x to 4x reductions now standard, and will continue to be a key element for success even with EUV in the future.
However, to achieve production-level success with multiple patterning engineers must understand and control inherent process variations that result from increasing number of process steps. The basic challenge is that with more process steps, there are more sources of variation.
In self-aligned multiple patterning schemes, critical dimension (CD) variability is impacted by variation not only from litho, but also from etch and deposition. For example, in self-aligned quadruple patterning, variations from litho, deposition, and etch could result in three different CDs, an undesired result known as pitch walking. To meet scaling requirements, variation from each step must be reduced in order to minimize pitch walking and produce the minimum on-chip device variation.
There are multiple sources of variability to be managed: within die, within wafer, from wafer to wafer, and from tool to tool. Within a die, the primary sources of variations come from geometry, pattern loading, and line edge roughness (LER). Within a wafer, variations are caused by the electrical and chemical gradients from center to edge across the wafer during processing. Wafer-to-wafer and tool-to-tool variations are determined by how tightly the hardware and process are controlled. Reactors are highly sophisticated and complex machines with countless sources of variability.
Continue reading at the EE Times website.