With the new year underway, you may be wondering what lies ahead for the semiconductor world. Once again, Solid State Technology has checked in with industry leaders for their thoughts on the outlook for the upcoming year. For 2016, those viewpoints were gathered from various sectors, including equipment manufacturers, component suppliers, market research firms, and consulting companies.
There were several technology-related predictions. Increasing demand for mobile products and the emergence of Internet of Things (IoT) applications will drive significant growth for advanced packaging, and the device test segment will expand to address new 5G communications and IoT needs. In addition, some of the contributors suggested that manufacturing requirements for IoT, MEMS, and other devices that don’t require leading-edge capability will lead to a resurgence of support for and retooling of 200 mm product lines. When it came to economics, semiconductor materials was a focus area. One author called out the automotive and IoT segments as new market drivers for materials. Another introduced a direct materials intensity index, which highlighted a “major trend” that the value of chip manufacturing materials is rising, particularly for leading-edge devices.
On the wafer fabrication equipment side, Lam’s Rick Gottscho, executive vice president of Global Products, shared his thoughts on implementing industry technology inflections. While these advances offer the benefits of lower power, higher density, and more functionality, they also increase complexity and cost of production. Challenges include edge placement error and pitch walking for multiple patterning, critical dimension control in all directions for FinFETs, and uniform memory cell formation for 3D NAND. As Rick explained in the article, addressing these issues will require greater control of unit processes as well as the interaction between those processes, and finding solutions to reduce both variation and cost is essential to continue scaling.
Richard Gottscho, Ph.D., Executive Vice President, Global Products, Lam Research Corp.
2016 looks to be an exciting year as several key inflection technologies – including multiple patterning, FinFET, and 3D NAND – continue to move into high-volume manufacturing worldwide. While these inflections enable the continuation of Moore’s Law, the increasing number of steps and overall complexity add significantly to the challenge of reducing process-induced variation.
At the 10 nm node and below, edge placement error (EPE) is becoming a significant limitation to continued scaling. Historically, the degree of EPE was largely determined by misalignment in lithography overlay. Today, EPE can be dominated by other process components, and variations from both lithography and non-lithography steps are pushing EPE beyond the allowable design specifications. This is exacerbated by the adoption of multiple patterning techniques such as litho-etch-litho-etch. One way to reduce overlay errors is to decrease the mask count, for example, by advancing to next-generation EUV lithography. With or without EUV, improved on-product overlay can be achieved by reducing line edge roughness through etching- and deposition-induced smoothing.
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