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Lam Connects to the World’s Fastest Growing Microelectronics Market at SEMICON China

March 8, 2021
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Category:
Corporate

SEMICON China will connect technologists to the world’s fastest growing and most dynamic microelectronics market. Held at the Shanghai New International Exhibition Centre (SNIEC) on March 17-19, 2021, participants will connect, collaborate, and innovate with industry professionals.

Once again, Lam is proud to be a sponsor of SEMICON China, as well as the sponsor of the Grand Opening Keynote. Tim Archer, president and CEO, will help kick-off the event, sharing his thoughts on China’s critical role in driving growth in the semiconductor industry and his outlook on the opportunities ahead. In addition, Scott Meikle, senior vice president in Global Customer Operations, will join leaders throughout the industry in the Grand Opening Keynote, giving his perspective on the changing technological landscape and the company’s continued collaboration with partners to deliver breakthrough semiconductor advancements.

(Keynote) New Collaboration in the New Normal
Scott Meikle
Grand Opening Keynote
Wednesday, March 17, 3:05 PM

Concurrent with SEMICON China is the China Semiconductor Technology International Conference (CSTIC), one of the largest annual semiconductor technology conferences in China. Held on March 14-15 in Shanghai with a virtual forum through April 11, the conference will cover all aspects of semiconductor technology and manufacturing, including devices, design, lithography, integration, processes, emerging semiconductor technologies, and silicon material applications. Lam is pleased to be a sponsor of the China Semiconductor Technology International Conference (CSTIC). Following is a summary of Lam’s participation throughout the conference.

(Invited) Advancing to the Next Node and Competing Globally Using Virtual Fabrication
Joseph Ervin
Symposium IV: Thin Film, Plating and Process Integration
Sunday, March 14, 1:30 PM

(Keynote) The Latest Developments and Results in Advanced Technology Nodes Patterning
Rich Wise
Symposium II: Lithography and patterning and Symposium III: Dry & Wet Etch and Cleaning (joint session)
Sunday, March 14, 1:35 PM

(Keynote) Mass Metrology Solution for 3D Process-Monitoring
Jiangtao Hu
Symposium VI: Metrology, Reliability and Testing
Sunday, March 14, 1:35 PM

The Effect of Poly Corner Etch Residue on Advanced FinFET Device Performance
Wang QingPeng
Symposium I: Device Engineering and Memory Technology
Monday, March 15, 11:40 AM

Simulation-Assisted Ion Angle Tuning in High Aspect-Ration (HAR) Etch for Wafer Edge Bottom Etch Enhancement
Jingdong Yan
Symposium III: Dry & Wet Etch and Cleaning
Monday, March 15, 2:00 PM

Poster Session

The Influence of the Gap of CCP System on PECVD WDC Film Thickness Nu% and Profile
Liu Zheng Yang

Extreme Edge Uniformity Control Study in Poly-Si Planarization Etch
Minxiang Wang

Optimization of a Photoresist Trim Process with ICP Reactor
Tianyin Sun

Novel Wet Etch Technology of Film Uniformity Tuning Through EOS AUT System
Bowen Dai

FinFET Gate Etch Modeling by Coventor SEMulator3D
Hexin Zhou

Gate Cut Patterning Scheme Simulation and Defect Modelling by SEMulator3D
Sun Li Fei

HNA Wet Etching Optimization in Wafer Thinning of BSI Process
Peng Fei Lyu

Improving Sidewall Roughness Performance through Shorten Phase Time RAP Process on Syndion tool in Deep Silicon Etching
Sun Yiling

MRAM MTJ Ion Beam Etching Simulation
Caigan Chen

FinFET Work Function Metal Recess Loading Improvement
Caigan Chen

Si3N4 Plasma Etching Study for Optimized Morphology Performance
Quanbao Li

Line Etch with HBr Cure Uniformity Study in Plasma Etch
Xiaohui Ren

Silicon Wafer Cleaning Optimization with Ozonated DI Water
Jia Xu

Silicon Wafer Uniformity and Roughness Control by Spin Etch D and Spin Etch E on Wafer Thinning
Pin Chang Li

Etch Front Flatness Modification at Wafer Extreme Edge in a High Aspect Ratio Process
Junming Wang

High Aspect Ratio Silicon Etch with High Selectivity to Tungsten
Chun Gao

Peeling Defect Studying with N2/H2 Plasma during Carbon-based Recess Etch
Tao Ye

SPARC SiCO: New Contact Metal Liner in Logic Advanced Nodes
Cesar Ji

A Study of Post-Clean N2O Plasma Treatment for PECVD High Stress Silicon Oxide Film Thickness Uniformity Stability
Min Shudi

Selective Growth Delay Performance Study of WCN on Various Substrate
Ao Yang

Optimization of Selective Inhibition for Void-Suppressed Tungsten Gap-fill
Xin Gan

SiH4 Soak Impact on BEOL Cu RC Delay and Reliability
Jiang Yu

Complete schedules and registration information can be found on the SEMICON China website. We look forward to meeting with you at the show.

 

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