When they were first commercialized at the 22 nm node, finFETs represented a revolutionary change to the way we build transistors, the tiny switches in the “brains” of a chip. As compared to prior planar transistors, the fin, contacted on three sides by the gate, provides much better control of the channel formed within the fin. But, finFETs are already reaching the end of their utility as challenges mount at the 5- and 3-nm nodes.
With every node, device manufacturers scale transistors to deliver both a performance boost and power reduction at lower device area and cost – commonly referred to as PPAC (power, performance, area, cost) scaling. However, further reduction in finFET dimensions leads to limitations in the drive current and electrostatic control.
In planar transistors, the width of the channel could be increased to drive more current and switch on and off faster. However, evolution of CMOS designs to standard cells with lower track height means that there is less flexibility in fin dimensions. Single-fin devices at sub-5 nm nodes will be unable to provide enough drive current.
Furthermore, although three sides of the fin are controlled by the gate, there remains one side that isn’t controlled. As the gate length is reduced, it leads to greater short channel effects and more leakage through the uncontacted bottom of the device, and, as a result, smaller devices can’t meet power and performance goals.
Gate-all-around, or GAA transistors, are a modified transistor structure where the gate contacts the channel from all sides and enables continued scaling. Such transistors are referred to as gate-all-around, or GAA, transistors, and different variants have been proposed.
Early GAA devices will use vertically-stacked nanosheets. They are constructed of separate horizontal sheets, surrounded by gate materials on all sides. This provides improved channel control relative to finFETs. Unlike finFETs, where higher current requires multiple side-by-side fins, the current-carrying capacity of GAA transistors is increased by stacking a few nanosheets vertically, with gate material wrapped around the channels. The nanosheet dimensions can be scaled so that transistors can be sized for the specific performance required.
However, as with fins, the width and spacing of the sheets will drop as the technology scales and as our ability to print finer features continues to improve. At some point, the width of the sheet may be roughly the same as the thickness – at which point they resemble nanowires.
Nanosheets may be simple in concept, but they present new challenges for manufacturing. Some of those challenges revolve around fabricating the structure; others involve new materials needed to achieve PPAC scaling targets.
The main construction challenges arise as a result of the complex structure being built. The GAA transistors are fabricated by first growing a superlattice of alternating Si and SiGe epitaxial layers, which form the basis for the nanosheets. Critical steps include deposition of an inner dielectric spacer to protect the source/drain regions and define the gate width, as well as the channel release etch to remove the sacrificial layers. That space left by removal of the sacrificial layers then needs to be filled with the gate dielectric and metal including between the nanosheets. New materials are likely to be introduced for the gate metal. Cobalt is being evaluated by some manufacturers, with ruthenium, molybdenum, nickel, and various alloys under consideration.
GAA transistors will be the successors to FinFETs, with nanosheets evolving to nanowires. These GAA structures should carry through the advanced process nodes currently on the roadmap.
Transistor structures have come a long way from the early planar architectures. Those early pioneers would have been astounded at the evolution, and at the incredible smart and connected world they have enabled. We look forward to seeing what new end-user devices and capabilities the gate-all-around transistor will bring.