Used to extend the capabilities of conventional lithography, multiple patterning is a process of overlaying patterns of larger dimensions to achieve smaller and/or more tightly packed features. In part one of a two-part series published in EE Times India, Rick Gottscho, Lam’s corporate chief technology officer, provides a high-level look at this enabling technique and its key role in advancing chip manufacturing.
For decades, one of the major trends in electronics has been miniaturisation, which has helped pack in more functionality, extend battery life, and lower production costs per chip. Up until recently, the semiconductor industry has been able to meet consumer demands for smaller, more powerful products by scaling lithography capabilities to shrink integrated circuit (IC) feature dimensions. In conventional lithography, a wafer is coated with a light-sensitive material called photoresist, then light is streamed through a photomask (a pattern of transparent and opaque areas), causing only certain areas of the wafer to be exposed. In the case of positive photoresist, the exposed areas are subsequently etched away while the remaining areas are left intact, resulting in a set of features determined by the original photoresist pattern.
While this technique has been used successfully for many years, today’s advanced chip designs have smaller and denser features that require going beyond limits imposed by the wavelength of light used in conventional lithography. To create these chips, advanced patterning techniques overlay multiple patterns of larger dimensions to achieve smaller and/or more tightly packed features.
The most basic form of multiple patterning is double patterning—increasing feature density two-fold. One of the most common double patterning schemes is litho-etch-litho-etch (LELE), which involves two exposures and two etch steps. Using two distinct lithography steps allows for significant flexibility in design as each mask can be optimised independently. In this process, the complete photomask pattern is divided into two less feature-dense parts. The first pattern is transferred onto an underlying hardmask through lithography followed by etching, and then the process sequence is repeated for the second pattern. A key challenge with this technique is that the two patterns should be aligned perfectly but imperfections in overlay persist – nothing is perfect. Reducing overlay errors is a primary area of focus today. Otherwise, the resulting combined pattern can have significant relative displacement, leading to electrical yield issues.
Continue reading at the EE Times India website.
Stay tuned for part two, which will address overcoming process variation in multiple patterning.