Electrochemistry and solid state science and technology will be featured at the 235th ECS Meeting, to be held May 26–30 in Dallas, Texas. Over the week, nearly two thousand talks will be given on topics including dielectric materials, electronic devices and systems, and sensors. The international meeting also includes a technical exhibition, a professional development workshop, and networking opportunities for scientists, researchers, and engineers from academia, government laboratories, and industry.
A key area of research is electrochemical processes for interconnect fabrication, both in chips and in packaging applications. In chips, interconnects are the wiring schemes that move signals from one transistor to another; and as chip features get smaller, the use of electrochemical copper metallization for interconnects has become more challenging. In advanced wafer level packaging, conductive structures such as copper pillars are used to similarly move electrical signals from chip to chip, chip to board, etc. Lam is pleased to have two technical presentations on this important topic:
Die Level Model for Electroplated Copper Pillars
G. Graham, L. P. Chua, B. Buckalew, T. Ponnnuswamy, and S. Mayer (Lam Research)
Tuesday, May 28, 10:20 a.m.
Improved Copper Damascene Wires Using Direct Plate on Cobalt Process
J. Brogan, Y. Liu, M. M. Huie, J. D. Reid (Lam Research); J. Kelly (IBM Albany Nanotechnology Center); H. K. Shobha (IBM Research at Albany Nanotech); H. Huang (IBM Research, Albany); K. Motoyama (IBM Research at Albany Nanotech); and C. K. Hu (IBM T.J. Watson Research Center)
Wednesday, May 29, 2:00 p.m.
Complete schedules and registration information can be found on the 235th ECS Meeting website. We look forward to seeing you at the conference.