Joint research in the semiconductor industry often drives innovative solutions for future technology nodes and is particularly valuable for exploring options several generations – and years – ahead. At Lam Research, we have a successful history of collaborating with our customers, in academia, and in the industry – such as our work with long-time research partner imec. In fact, as a member of imec’s Supplier Hub, we recently co-developed a promising path to enabling interconnect scaling at the 7 nm node, as explained in the following announcement.
New Approach to Pave the Way for Advanced Interconnects Enabling Future Technology Nodes
EEE IITC, Grenoble (France)—May 19, 2015—During the IEEE IITC conference in Grenoble, the nanoelectronics research center imec and Lam Research Corporation today presented a novel bottom-up prefill technique for vias and contacts. The technique, based on Electroless Deposition (ELD) of Cobalt (Co) is a highly selective method resulting in void-free filling of via and contact holes. Potentially increasing the circuit performance, it is a promising path to scaling advanced interconnects and enabling future logic and DRAM nodes at the 7 nm node and below.