Test Your Knowledge of Semiconductor Terms

July 11, 2016
Category:
Industry, Technology

The semiconductor industry uses so many unique terms, it practically has its own language. To keep up on the latest developments, knowing that “language” can be really helpful. For instance, do you know your 3D NAND from your 3D IC? How about FEOL versus BEOL? Take our semiconductor industry vocabulary challenge below and see how you do. (HINT: Lam’s Technical Glossary can help!) We hope you have some fun, and you just might learn a few handy new words, too.

 

Semiconductor Industry Terms Challenge

 

1) Interconnect formation falls under which of the following areas of wafer processing?

A) BEOL
B) FEOL
C) LOL
D) MOL

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A – BEOL. Interconnect formation – creating the wiring that connects components in an integrated circuit – is part of back-end-of-line (BEOL) processes. Front-end-of-line (FEOL) processes form transistors and other circuit elements. Middle-of-line (MOL) processes create local electrical connections (contacts). Oh, and if you don’t know what LOL means, we’re afraid our Technical Glossary can’t help you.

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2) 3D NAND and 3D IC are the same thing.

A) True
B) False

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B – False. Although both terms involve three-dimensional (3D) architectures, 3D NAND is a form of flash memory, while 3D IC refers to an integrated circuit (IC) formed by stacking wafers and/or dies. Both ease the challenge of packing more devices into less space by building vertically. To learn more about 3D NAND, check out our Tech Brief: Memory “Grows Up” with 3D NAND

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3) What does HAR mean?

A) Something a pirate says
B) High and rectangular
C) Hidden angle re-entrant
D) High aspect ratio

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D – High aspect ratio. Aspect ratio refers to how tall an object is in relation to its width. A shape considered high aspect ratio (HAR) would have a much greater height compared to its width. In the semiconductor industry, aspect ratios of some device features can be as much as 50:1 or greater, which makes them challenging to manufacture. For some perspective on how extreme these geometries can be, take a look at our blog story, A Sense of Scale: How High Is High? 

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4) What does the acronym “FOUP” stand for?

A) Fab Operating Unit Process
B) Foreign Objects Under Protection
C) Front-Opening Unified Pod
D) Flatten Out Under Pressure

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C – Front-Opening Unified Pod. A FOUP is a specialized controlled-environment carrier used to transport semiconductor wafers between processing tools in order to minimize contamination exposure. They became commonplace when the industry moved to 300-mm diameter wafers and were designed to handle the larger, more fragile substrates.

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5) Which of the following terms are NOT used in relation to multiple patterning?

A) DPT
B) LELE
C) MSSD
D) SAQP

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C – MSSD. MSSD (Multi-Station Sequential Deposition) is Lam’s innovative tool architecture with multiple deposition stations designed for excellent film uniformity and high productivity. LELE (litho/etch/litho/etch) is a type of DPT (double patterning technology), which as the name implies, is used to double pattern density. SAQP (self-aligned quadruple patterning) is a spacer-based multiple patterning technique that quadruples the pattern density. Learn more about these patterning strategies in our Tech Brief: Multiple Patterning Makes Miniaturization Possible.

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6) Which of the following processes uses plasma?

A) Deposition
B) Etch
C) Clean
D) A and B only
E) A, B, and C

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E – A, B, and C. A plasma is a state of matter made up of ions, electrons, and reactive neutral components created by sending a charge through a gas. Plasmas are used for many thin film deposition processes, such as PECVD (plasma-enhanced chemical vapor deposition). They are also commonly used in plasma etch, where chemical and/or physical (ion bombardment) mechanisms selectively remove material from the wafer. This selective removal also makes plasmas a useful technology for wafer cleaning, such as bevel clean.

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7) All of the following are types of memory technologies: Flash, NAND, DRAM, MRAM.

A) True
B) False

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A – True. DRAM (dynamic random access memory) is a type of volatile memory, which needs power to retain data. Flash (including NAND) and MRAM (magnetoresistive random-access memory) are types of non-volatile memory, meaning they do not require power to retain stored information. MRAM uses magnetic elements rather than conventional electric charges to store data.

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8) Which of the following represents the smallest unit of measure?

A) Angstrom
B) Micron
C) Millimeter
D) Nanometer

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A – Angstrom. An angstrom is a unit of length equal to 1 x 10-10 (0.0000000001) meters. A nanometer represents 1 x 10-9 meters. A micron (also known as a micrometer) represents 1 x 10-6 meters, while a millimeter represents 1 x 10-3 meters. Advanced semiconductor devices can have feature sizes on the order of nanometers, requiring control to the angstrom level! To get a sense of just how small this really is, see our blog article, A Sense of Scale: How Small Is Small?

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9) The use of ALD and ALE is growing because:

A) Who can resist a good ALE?
B) They help reduce process variability for extremely small features
C) The industry is shifting to extremely small silicon wafers
D) B and C

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B – They help reduce process variability for extremely small features. ALD (atomic layer deposition) lays down films a few atomic layers at a time. Similarly, ALE (atomic layer etching) removes material a few atomic layers at a time. This makes these technologies particularly useful for applications that require extreme control and highly uniform results. To learn more about ALD and ALE work, see our video in the article Building Chips a Few Atoms at a Time.

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10) Which of the following types of uniformity are important for managing yield?

A) Within a chip or die
B) Across a wafer
C) From one wafer to another wafer
D) B and C only
E) A, B, and C

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E – A, B, and C. To maximize yield and device performance of today’s advanced chips, all three types of uniformity must be managed: within a chip or die (from feature to feature), across a wafer (from die to die), and from one wafer to another wafer (lot to lot, chamber to chamber, tool to tool, fab to fab). Variability control is especially critical as device geometries shrink and the number of process steps increases.

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