Tech Brief: FinFET Fundamentals

September 12, 2016
Industry, Technology

Transistors are at the heart of our cherished electronics. Millions, or even billions, of these tiny switches go to work for us when we check our mobile phones, use our computers, start our automobiles, or play on our gaming consoles. But what exactly are transistors and how do they work? And how have they changed over the years? Here we take a look at some transistor fundamentals, including the operation of a field-effect transistor (FET), as well as the FinFET technology inflection that is enabling even smaller, more powerful semiconductor chips.


Transistor Basics

A transistor is essentially a switch (or an amplifier – but let’s concentrate on its switching capability). Just like an old-fashioned light switch, a transistor has two basic states: on and off. A FET uses an electric field to control the electrical conductivity through a channel. Similar to the way a gate in a fence permits or blocks the passage of people, a FET gate permits or blocks the flow of electrons between the source and the drain. In one common type (n-channel), electrons flow easily from source to drain when a positive voltage is applied to the gate. If the gate-to-source voltage is negative, then the conductive channel is blocked and electron flow in the transistor is switched off.

Traditionally, FETs are fabricated directly on silicon wafers. An insulating dielectric layer (such as silicon dioxide) is grown across the surface of the wafer and will become the gate dielectric. A conductive layer (such as polysilicon or a metal) is deposited on the dielectric and will eventually become the gate electrode. Lithography is used to transfer the desired pattern onto the wafer, then parts of that pattern are etched to define gate and to expose locations that will become the source and drain. Next, ions (such as boron or phosphorous) are implanted into the source and drain areas. This device structure is also known as “planar gate.”

The gate in a planar field-effect transistor blocks current or allows it to flow


FET Scaling Challenges

For many generations, the switching speed – and hence the performance of the transistor – could be increased by shrinking the gate length (L) and by applying stress to improve the channel mobility. However, these strategies ran into difficulties when the gate reached a length of around 20 nm. At dimensions that small, transistor performance was affected by short-channel effects. For example, current could leak between the source and drain even when flow should have been turned off. This and other technical challenges drove engineers to look at alternative transistor designs.


Short-channel effects, such as leakage current, occur when the gate length becomes too short



A 3D Scaling Solution

One way to regain control over channel current flow is to raise the channel above the plane of the silicon, creating the “fin” that is characteristic of the FinFET design. The gate wraps around the channel on three sides of the raised fin, instead of only across its top. The greater surface area between gate and channel provides better control of the electric field and thereby reduces leakage in the “off” state. Another advantage is that a lower gate voltage is needed to operate the transistor. The result is a transistor with better performance and reduced power consumption.

The three-dimensional FinFET geometry is a key technology inflection that also provides a possible roadmap to further scaling. By building the transistor vertically, chipmakers are able to continue shrinking dimensions and packing more components onto a chip. Designers can also choose to increase the height of the fin, which allows higher current flow through the channel without taking up more room on the die.


Comparison of planar transistor and FinFET architectures



FinFET Fabrication Challenges

While FinFETs offer power, performance, and scaling solutions, they are not without manufacturing challenges. In today’s leading-edge technologies, self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) are used to create the fin structure. In these methods, spacers are deposited on the sidewalls of a sacrificial structure, which is later removed by etching. The spacers are ultimately removed, leaving the desired fins. Throughout this process, the height and width of each fin must be tightly controlled since these critical dimensions affect device performance.

Good etch selectivity is needed to remove residue from the corners of the fin and gate. If not properly controlled, the energetic ions used to remove this corner residue may cause damage to exposed surfaces. The thin, fragile fin and gate structures are also a challenge for wet clean processes: particles must be removed as completely as possible without causing material loss and without features collapsing during wafer drying.

Gate formation brings additional difficulties, and each aspect of the gate must meet exacting requirements for the transistor to perform correctly. One key step is filling the gate with a conductive material that has low electrical resistivity, such as tungsten. Ideally, this tungsten metal can be deposited without leaving any holes (voids), which becomes increasingly difficult as the structure gets narrower.

Fortunately, the industry has developed a range of solutions that together have allowed FinFETs to move into production. In fact, FinFETs were first commercialized in 2011 and are now being produced by all leading manufacturers. Advanced deposition, etch, and clean solutions all play a critical role in enabling this significant transition.


Some of the key process challenges in creating FinFET structures



Next on the Transistor Roadmap?

The FinFET architecture has helped extend Moore’s Law, with designs currently stretching to the 10 nm technology node. While that is an amazing achievement, the industry is already working on ways to continue transistor scaling. New materials, such as germanium, are being explored for the fin in order to improve channel mobility and hence transistor speed. Others are testing FETs with a gate surrounding the channel on all four sides. This “gate-all-around” or “nanowire” approach is a concept being investigated for the 7 nm or 5 nm node. Beyond that, are single-atom transistors in our future? We look forward to seeing what our industry creates next – and the amazing new electronic products that these “super chips” may enable.


Future transistor structures may have a new fin material or a “gate-all-around” design



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