Latest Developments in Advanced Lithography on Stage at SPIE Symposium

February 15, 2016
Category:
Technology

Is Moore’s Law still on track? Can transistors, already more than a thousand times smaller than a grain of sand, continue to get even smaller? This is the challenge faced by the advanced patterning community, which will gather at the upcoming SPIE Advanced Lithography Symposium in San Jose, CA, February 21-25.

Patterning – the set of steps that transfers chip designs onto wafers – continues to be one of the most challenging areas of semiconductor manufacturing, driving innovations in both conventional and alternative technologies. Today’s devices often have feature sizes smaller than can be created with a single patterning cycle using conventional lithography. New materials, new technologies, and innovative processes such as multiple patterning will continue to grow in importance as device features shrink to atomic-scale dimensions.

Lam’s Rick Gottscho, executive vice president of Global Products, will give a plenary talk on multiple patterning and will discuss strategies for reducing process-induced variability. In addition, Lam is once again pleased to be the sponsor for the Advanced Etch Technology for Nanopatterning conference. Topics covered include overviews of nanopatterning challenges, patterning integration schemes, and emerging etch technologies. You can hear about some of the latest advances from Lam and our collaborators at several of the symposium’s conferences, as listed below. We look forward to seeing you at the event.

 

Plenary

Minimizing Process-Induced Variability in Multiple Patterning
Richard A. Gottscho (Lam Research)
Monday, February 22, 9:10 AM

Advanced Etch Technology for Nanopatterning (Conference 9782)

(Invited) Self-Aligned-Quadruple-Patterning for N7/N5 Silicon Fins
E. Altamirano-Sánchez, T.S. Zheng, A.G. Demirkol, G.F. Lorusso, T. Hopf, J.-C. Everat, W. Clark, (IMEC); D. Sobieski, F.-S. Ou, D. Hellin (Lam Research)
Tuesday, February 23, 11:00 AM

(Invited) Interactions between Plasma and Block Copolymers Used in Directed Self-Assembly Patterning
S. Sirard (Lam Research); L. Azarnouche (UC Berkeley); E. Gurer (Lam Research); W.J. Durand, M. J. Maher, K. Mori, G. Blachut, D. Janes, Y. Asano, Y. Someya (UT Austin); D. Hymes (Lam Research); D.B. Graves (UC Berkeley); C.J. Ellison, C.G. Willson (UT Austin)
Tuesday, February 23, 4:30 PM

450 mm Etch Process Development and Process Chamber Evaluation Using 193i DSA Guided Pattern
W. Collison (SUNY Polytechnic Institute); Y.-C. Lin (TSMC); S. W. Dunn (SUNY Polytechnic Institute); H. Takikawa, J. Paris (Hitachi High Technologies); L. Chen, T. Detrick (Applied Materials); J. Belen, G. Stojakovic, M. Goss (Lam Research); N. Fish (Intel); M.-J. Park (Samsung); C.-M. Sun (TSMC); M. Kelling (GLOBALFOUNDRIES); P. Lin (TSMC)
Tuesday, February 23, 5:30 PM

Optical Microlithography (Conference 9780)

Ultimate Intra-wafer Critical Dimension Uniformity by Using Co-optimized Lithography and Etch Tool Corrections
M. Kubis, L. Reijnen, K. Viatkina, M. Luca, C. Chahine, J. Mulkens, M. V. Dusa (ASML); R.J. Wise, D. Hellin, B. Kam, D. Sobieski, J. Vertommen, G.A. Dixit, N. Shamma (Lam Research); P. Jaenen, P. Leray (IMEC)
Tuesday, February 23, 11:50 AM

Alternative Lithographic Technologies (Conference 9777)

Directed Self-assembly of Silicon-containing Block Copolymers for 20 nm Lithography
G. Blachut, C. Grant Willson (UT Austin); S. Sirard (Lam Research); M. J. Maher, Y. Asano, Y. Someya, A.P. Lane, W.J. Durand, C.J. Ellison (UT Austin); D. Hymes (Lam Research); R. Gronheid (IMEC)
Tuesday, February 23, 2:40 PM

Metrology, Inspection, and Process Control for Microlithography (Conference 9778)

Improving Scanner Wafer Alignment Performance Using Mark Optimization
C. Jehoul, Philippe Leray (IMEC); R.J. Socha, B. Menchtchikov, E.R. Kent, H. Schoonewelle, S. Raghunathan, P. Tinnemans, P. Tuffy (ASML); R.J. Wise (Lam Research)
Wednesday, February 24, 6:00 to 8:00 PM poster session

Advances in Patterning Materials and Processes (Conference 9779)

Access to 5 nm Features with DSA Topcoat System
Y. Asano, M.J. Maher, G. Blachut (UT Austin); S. Sirard (Lam Research); Y. Someya, A.P. Lane, W.J. Durand, C.J. Ellison, C. Grant Willson (UT Austin)
Wednesday, February 24, 5:30 PM

Trilayer Rework Optimization to Overcome Advanced Technologies Challenges
P. Bar (STMicroelectronics); D. Mattson, M. Massardier (Lam Research); N. Chessel, F. Di-Zanni, S. Audran, P. Chevalier, (STMicroelectronics); D. Cheung (Lam Research); C.-T. Richard (STMicroelectronics)
Thursday, February 25, 8:20 AM

 

Complete schedules and registration information can be found on the SPIE Advanced Lithography website.

 

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