Journal Papers Showcase Research at Lam

January 11, 2016
Category:
Technology

From materials research to plasma fundamentals, Lam’s technologists are contributing to practical and theoretical developments in their fields. One way they help advance technology and expand scientific knowledge is by publishing in peer-reviewed journals, often in collaboration with academic researchers. See below for some of our recent publications from the technical literature.

 

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Leakage Current Mechanisms and Their Dependence on Composition in Silicon Carbonitride Thin Films
Vishnuvardhanan Vijayakumar and Bhadri Varadarajan, Lam Research Corp.
Mater. Res. Express 2 (2015) 046302

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Abstract: Electrical conduction in amorphous silicon carbonitride (a-SiCN:H) thin films deposited by plasma enhanced chemical vapor deposition (PECVD) is investigated for varying carbon to nitrogen ratios at room temperature. Films deposited with a lower carbon/nitrogen ratio showed two modes of electrical conduction; namely, Schottky emission mode below 2.3 MV cm−1 electric field and Poole–Frenkel mode from 2.3 MV cm−1 up to the breakdown field. Films with higher carbon/nitrogen ratios showed only Poole–Frenkel mode of conduction throughout the entire range of operation up to the breakdown field. The carbon rich films exhibited higher leakage currents attributed to its shallow defect energy levels leading to its higher Poole–Frenkel conductivity.

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Work Function Tuning of Plasma-Enhanced Atomic Layer Deposited WCxNy Electrodes for Metal/Oxide/Semiconductor Devices
Oren Zonensain (1), Sivan Fadida (1), Ilanit Fisher (2), Juwen Gao (2), Kaushik Chattopadhyay (2), Greg Harm (2), Tom Mountsier (2), Michal Danek (2), Moshe Eizenberg (1)
1-Technion—Israel Institute of Technology, 2-Lam Research Corp.
Appl. Phys. Lett. 106, 082107 (2015)

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Abstract: One of the main challenges facing the integration of metals as gate electrodes in advanced MOS devices is control over the Fermi level position at the metal/dielectric interface. In this study, we demonstrate the ability to tune the effective work function (EWF) of W-based electrodes by process modifications of the atomic layer deposited (ALD) films. Tungsten carbo-nitrides (WCxNy) films were deposited via plasma-enhanced and/or thermal ALD processes using organometallic precursors. The process modifications enabled us to control the stoichiometry of the WCxNy films. Deposition in hydrogen plasma (without nitrogen based reactant) resulted in a stoichiometry of WC0.4 with primarily W-C chemical bonding, as determined by x-ray photoelectron spectroscopy. These films yielded a relatively low EWF of 4.2 ± 0.1 eV. The introduction of nitrogen based reactant to the plasma or the thermal ALD deposition resulted in a stoichiometry of WC0.1N0.6–0.8 with predominantly W-N chemical bonding. These films produced a high EWF of 4.7 ± 0.1 eV.

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Ultrathin Graphene and Graphene Oxide Layers as a Diffusion Barrier for Advanced Cu Metallization
Jae Hoon Bong (1), Seong Jun Yoon (1), Alexander Yoon (2), Wan Sik Hwang (3), Byung Jin Cho (1)
1-KAIST, 2-Lam Research Corp., 3-Korea Aerospace Univ.
Appl. Phys. Lett. 106, 063112 (2015)

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Abstract: We report on the diffusion barrier properties of chemical-vapor-deposition grown graphene, graphene oxide, and reduced graphene oxide (rGO) for copper metallization in integrated circuits. Single-layer graphene shows the best diffusion barrier performance among the three but it has poor integration compatibility, displaying weak adhesion and poor nucleation for Cu deposition on top of it. Within the allowable thermal budget in the back-end-of-line process, rGO in a range of 1 nm thickness shows excellent thermal stability with suitable integration compatibility at 400 °C for 30 min. The diffusion barrier property was verified through optical, physical, and chemical analyses. The use of an extremely thin rGO layer as a Cu barrier material is expected to provide an alternative route for further scaling of copper interconnect technology.

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Overview of Atomic Layer Etching in the Semiconductor Industry
Keren J. Kanarik, Thorsten Lill, Eric A. Hudson, Saravanapriyan Sriraman, Samantha Tan, Jeffrey Marks, Vahid Vahedi, Richard A. Gottscho, Lam Research Corp.
J. Vac. Sci. Technol. A, Vol. 33, 020802 (2015)

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Abstract: Atomic layer etching (ALE) is a technique for removing thin layers of material using sequential reaction steps that are self-limiting. ALE has been studied in the laboratory for more than 25 years. Today, it is being driven by the semiconductor industry as an alternative to continuous etching and is viewed as an essential counterpart to atomic layer deposition. As we enter the era of atomic-scale dimensions, there is need to unify the ALE field through increased effectiveness of collaboration between academia and industry, and to help enable the transition from lab to fab. With this in mind, this article provides defining criteria for ALE, along with clarification of some of the terminology and assumptions of this field. To increase understanding of the process, the mechanistic understanding is described for the silicon ALE case study, including the advantages of plasma-assisted processing. A historical overview spanning more than 25 years is provided for silicon, as well as ALE studies on oxides, III–V compounds, and other materials. Together, these processes encompass a variety of implementations, all following the same ALE principles. While the focus is on directional etching, isotropic ALE is also included. As part of this review, the authors also address the role of power pulsing as a predecessor to ALE and examine the outlook of ALE in the manufacturing of advanced semiconductor devices.

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Highly Selective Directional Atomic Layer Etching of Silicon
Samantha Tan, Wenbing Yang, Keren J. Kanarik, Thorsten Lill, Vahid Vahedi, Jeff Marks, Richard A. Gottscho, Lam Research Corp.
ECS J. Solid State Sci. Technol. Vol. 4, Issue 6, N5010-N5012 (2015)

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Abstract: Following Moore’s Law, feature dimensions will soon reach dimensions on an atomic scale. For the most advanced structures, conventional plasma etch processes are unable to meet the requirement of atomic scale fidelity. The breakthrough that is needed can be found in atomic layer etching or ALE, where greater control can be achieved by separating out the reaction steps. In this paper, we study selective, directional ALE of silicon using plasma assisted chlorine adsorption, specifically selectivities to bulk silicon oxide as well as thin gate oxide. Possible selectivity mechanisms will be discussed.

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Control of Ion Energy and Angular Distributions in Dual-Frequency Capacitively Coupled Plasmas Through Power Ratios and Phase: Consequences on Etch Profiles
Yiting Zhang (1), Mark J. Kushner (1), Saravanapriyan Sriraman (2), Alexei Marakhtanov (2), John Holland (2), and Alex Paterson (2)
1-Univ. of Michigan, 2-Lam Research Corp.
J. Vac. Sci. Technol. A, Vol. 33, 031302 (2015)

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Abstract: Anisotropic etching, enabled by energetic ion bombardment, is one of the primary roles of plasma–assisted materials processing for microelectronics fabrication. One challenge in plasma etching is being able to control the ion energy-angular distributions (IEADs) from the presheath to the surface of the wafer which is necessary for maintaining the critical dimension of features. Dual frequency capacitive coupled plasmas (DF-CCPs) potentially provide flexible control of IEADs, providing high selectivity while etching different materials and improved uniformity across the wafer. In this paper, the authors present a computational investigation of customizing and controlling IEADs in a DF-CCP resembling those industrially employed with both biases applied to the substrate holding the wafer. The authors found that the ratio of the low-frequency to high-frequency power can be used to control the plasma density, provide extra control for the angular width and energy of the IEADs, and to optimize etch profiles. If the phases between the low frequency and its higher harmonics are changed, the sheath dynamics are modulated, which in turn produces modulation in the ion energy distribution. With these trends, continuously varying the phases between the dual-frequencies can smooth the high frequency modulation in the time averaged IEADs. For validation, results from the simulation are compared with Langmuir probe measurements of ion saturation current densities in a DF-CCP.

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Dewetting Model Study on a Spinning Substrate – Challenges for Low Chemical Consumption
Ken-ichi Sano, David Mui, Mark Kawaguchi, Lam Research Corp.
ECS Trans. Vol. 69, Issue 8, 139-144 (2015)

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Abstract: A model is proposed to describe the wetting and dewetting dynamics on a spinning wafer with a non-wetting surface. The model is based on the dynamic balance between the wetting and dewetting velocities. The proposed model predicts a theoretical lower limit for the media flow rate to completely wet a wafer surface as a function of the contact angle and wafer rotational speed. The model predictions are found to agree reasonably well with experimental results. The model is also used to develop a low flow process for the removal of titanium nitride. A 66% flow rate reduction is achieved in comparison with the baseline process.

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Using Deionized Water to Remove Polystyrene Latex Particles from Oxide Layer by Single-Wafer Spin Processing
Kei Kinoshita, Philipp Engesser, Harald Okorn-Schmidt, Lam Research Corp.
ECS J. Solid State Sci. Technol. Vol. 3, Issue 11, P357-P362 (2014)

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Abstract: Residual particles significantly degrade the performance of large-scale integrated circuits; hence, the methods and efficiencies of particle-removal technologies for semiconductor wafer-cleaning processes are continuously being improved. This paper reports a deionized water (DIW)-based approach that significantly improves the particle removal efficiency (PRE) of polystyrene latex (PSL) particles from oxide surfaces. PSL particles are generally very difficult to remove from silicon oxide surfaces using DIW alone. We previously attempted to improve the PSL removal rate with DIW by increasing the wafer rotation speed and the medium flow rate in single-wafer spin processing. However, the maximum PRE was below 50% (PSL, 500 nm spheres). This study reports on the improvement of the PRE to >98.0% by combining a DIW clean with a very low wafer rotation speed (10 rpm) and a very low DIW flow rate (200 ml/min). The spatial distribution of the PRE matches that of the calculated capillary numbers across the wafer. We propose that the low wafer rotation speed and DIW flow rate impact the capillary number, allowing the DIW to percolate between the PSL particles and the oxide surface. Particles uplifted by this process become suspended in or on top of the liquid layer covering the wafer, and are removed when the rotation speed of the wafer is increased during the final drying process.

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Improvement in Surface Grinding Damage in Silicon Wafers by Chemical Spin Etching
Kei Kinoshita, Lam Research Corp.
ECS J. Solid State Sci. Technol. Vol. 3, Issue 4, Q61-Q64 (2014)

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Abstract: Understanding damage caused by mechanical grinding is required for wafer thinning processes, because such damage significantly affects device performance in large-scale integrated circuits. Herein, in-depth analysis of damage caused by mechanical grinding was conducted by measuring minority carrier lifetime and by the photoacoustic displacement (PAD) technique, which are highly sensitive and quantitative methods for measuring damage. Previous low-sensitivity damage measurements indicate that grinding damage is distributed within a 5-μm-thick surface layer. However, although a 10-μm-thick surface layer is removed by chemical spin etching (CSE), the minority carrier lifetime remains low. This result suggests that significant damage still exists in layers deeper than 10 μm. After etching a 200-μm-thick layer, PAD measurements show that displacement at the surface recovers to 20 pm, which is the level of undamaged silicon. While minority carrier lifetime gradually increases with increased etching, this lifetime remains low after removing a 100-μm-thick strain layer. The minority carrier lifetime reaches that of defect-free silicon after removing a 300-μm-thick layer. These results clearly indicate that deep damage (i.e., depth of 200 μm) is caused at the silicon surface by conventional mechanical grinding. Additionally, we conclude that the CSE process is useful for thinning silicon wafers without inducing damage or strain.

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